Performance Evaluation of Bypassing Array Multiplier with Optimized Design
نویسندگان
چکیده
منابع مشابه
Low Power Multiplier Design with Improved Column Bypassing Scheme
Power, speed and area are prime design constraints for portable electronics devices and signal processing applications. Multiplier plays an important role in DSP applications. In this paper, a low power and high speed multiplier with improved column bypassing scheme is presented. Primary power reduction is obtained by disabling the supply voltage of non-functional blocks when the operands of th...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2011
ISSN: 0975-8887
DOI: 10.5120/3387-4701